Abstract: A new fast ray - patch intersection algorithm is presented. The algorithm correctly handles all ray - patch intersections. A number of parameters are derived from a numerical analysis of the algorithm and the datapad is resynthesized for higher accuracy. A global architecture for an ASIC for intersecting a ray with a Bézier patch is presented. It is shown that a cache combined with pre pads can reduce the required memory considerable with an extremely small performance penalty. Attention will be paid to the scheduling and control problem. Several high level optimizations are presented that make efficient scheduling possible and decrease the calculation time considerably.