An Architecture for High-Performance 2-D Image Display
Stephen D. Jordan, Philip E. Jensen, Barthold B. A. Lichtenbelt
Eurographics Workshop on Graphics Hardware, 1996, pp. 39--45.
Abstract: Image processing operations can be divided into two classes, those pre-processing operations that are market- and application-specific, and those widely-used operations that are useful in any application that requires the display of two-dimensional images. In the interest of achieving real-time rates for the broader class of 2-D image display operations, Hewlett-Packard has developed a hardware accelerator called VISUALIZE-IVX. It is capable of scaling, rotating, mirroring, translating and filtering lk-by-lk output images at greater than 30 frames/sec while simultaneously enhancing image brightness and contrast. This paper describes the pipelined architecture used to achieve this performance on a desktop computer. The Architecture makes use of a hybrid mapping scheme for geometric transformations. Also a unique memory device was designed that minimizes local image buffers while eliminating the need to resend pixels from main memory. A recently developed method of extending the filtering capabilities, that may be incorporated into future products, is also presented.
Article URL: http://diglib.eg.org/EG/DL/WS/EGGH/EGGH96/039-045.pdf
BibTeX format:
@inproceedings{Jordan:1996:AAF,
  author = {Stephen D. Jordan and Philip E. Jensen and Barthold B. A. Lichtenbelt},
  title = {An Architecture for High-Performance 2-D Image Display},
  booktitle = {Eurographics Workshop on Graphics Hardware},
  pages = {39--45},
  year = {1996},
}
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