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On the Design of a Real-Time Volume Rendering Engine
J. Smit, N. J. Wessels, A. van den Horst, M. J. Bentum
Eurographics Workshop on Graphics Hardware, 1992, pp. 70--76.

Abstract: An architecture for a Real-Time Volume Rendering Engine is given capable of computing750x750x512 samples from a 3D dataset at a rate of 25 images per second.The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISe-processors. An plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. The interpolator is now back from production. It has been tested an complied with our specifications.

Article URL: http://diglib.eg.org/EG/DL/WS/EGGH/EGGH92/070-076.pdf

BibTeX format:

@inproceedings{Smit:1992:OTD,
  author = {J. Smit and N. J. Wessels and A. van den Horst and M. J. Bentum},
  title = {On the Design of a Real-Time Volume Rendering Engine},
  booktitle = {Eurographics Workshop on Graphics Hardware},
  pages = {70--76},
  year = {1992},
}

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