Latency- and Hazard-Free Volume Memory Architecture for Direct Volume Rendering
M. de Boer, A. Gropl, J. Hesser, R. Männer
Eurographics Workshop on Graphics Hardware, 1996, pp. 109--119.
Abstract: The computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by high-speed rendering architectures. However the increasing processor speed makes a performance bottleneck obvious - the volume memory. This paper describes a volume memory architecture that achieves at least a tenfold speed-up in read-out rate with moderate additional hardware. It has been simulated successfully. A multi-level cache system is used with software prefetching and latency hiding. Pre- and postcaches additionally speed up the read-out rate so that a 5123 data set stored in a single memory module can be rendered at 3.125 Hz.
Article URL: http://diglib.eg.org/EG/DL/WS/EGGH/EGGH96/109-119.pdf
BibTeX format:
@inproceedings{deBoer:1996:LAH,
  author = {M. de Boer and A. Gropl and J. Hesser and R. Männer},
  title = {Latency- and Hazard-Free Volume Memory Architecture for Direct Volume Rendering},
  booktitle = {Eurographics Workshop on Graphics Hardware},
  pages = {109--119},
  year = {1996},
}
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