Abstract: Contemporary graphics architectures are based on a hardware-supported geometric pipeline, a rasterizer, a z-buffer and two frame buffers. Additional pixel memory isused for alpha blending and for storing logical information. Although their functionality is growing it is still limited because of the fixed use of pixel memory and there stricted set of operations provided by these architectures. A new class of graphics algorithms that considerably extends the current technology is based on a moreflexible use of pixel memory, not supported by current architectures. The M-Buffer architecture described here divides pixel memory into general-purposebuffers, each associated with one processor. Pixel data is broadcast to all buffers simultaneously. Logical and numeric tests are performed by each processor and theresults are broadcast and used by all buffers in parallel to evaluate logical expressionsfor the pixel update condition.The architecture is scalable by addition of buffer-processors, suitable for pixel parallelization,and permits the use of buffers for different purposes. The architecture, its functional description, and a powerful programming interface are described.