Abstract: In this paper we explore strategies for screen-space tiling in programmable rendering pipelines on modern GPUs. The need for tiling arises from the inherent unpredictability of workload size in many rendering pipelines. While it additionally also reduces the bandwidth demand of the rendering operations and increases locality of memory accesses, we focus on meeting resource limits in programmable rendering. We show that by ensuring load balance, dynamic tiling in a modern programmable GPU pipeline delivers performance improvements over traditional static tiling techniques. We explore prediction and splitting algorithms for adaptive tiling schemes and demonstrate that even approximate estimates of tile bounds can reduce tiling overhead. We evaluate the above optimizations by implementing them for a three GPU-based tiled renderers while keeping our observations general enough so that they are applicable to other forms of rendering as well.